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respectively). This master clock input is then provided to the CODEC and the XS1
device.
3.8.1 Port Configuration (CODEC Slave)
The default software configuration is CODEC Slave (XS1 master). That is, the XS1
provides the BCLK and LRCLK signals to the CODEC.
XS1 ports and XS1 clocks provide many valuable features for implementing I2S.
This section describes how these are configured and used to drive the I2S interface.
L8A-64-TQ128
p_mclk
p_sdin
clk_audio_mclk
clk_audio_bclk
Audio master clock
CODEC
p_bclk
p_lrclk
p_sdout
Figure 12:
Ports and
Clocks
(CODEC slave)
The code to configure the ports and clocks is in the
ConfigAudioPorts()
function.
Developers should not need to modify this.
The L-Series device inputs MCLK and divides it down to generate BCLK and LRCLK.
To achieve this, MCLK is input into the device using the 1-bit port
p_mclk
. This
is attached to the clock block
clk_audio_mclk
, which is in turn used to clock the
BCLK port,
p_bclk
. BCLK is used to clock the LRCLK (
p_lrclk
) and data signals
SDIN (
p_sdin
) and SDOUT (
p_sdout
). Again, a clock block is used (
clk_audio_bclk
)
which has
p_bclk
as its input and is used to clock the ports
p_lrclk
,
p_sdin
and
p_sdout
. The preceding diagram shows the connectivity of ports and clock blocks.
p_sdin
and
p_sdout
are configured as buffered ports with a transfer width of 32,
so all 32 bits are input in one input statement. This allows the software to input,
process and output 32-bit words, whilst the ports serialize and deserialize to the
single I/O pin connected to each port.
Buffered ports with a transfer width of 32 are also used for
p_bclk
and
p_lrclk
.
The bit clock is generated by performing outputs of a particular pattern to
p_bclk
to toggle the output at the desired rate. The pattern depends on the divide between
MCLK and BCLK. The following table shows the pattern for different values of this
divide:
REV 6.1
- USB Audio Design Guide 1
- SYNOPSIS 2
- Table of Contents 3
- 1 Overview 5
- 2 Hardware Platforms 6
- 3 Software Architecture 9
- 3.2 Binary Naming 10
- 3.4 USB Audio Class Support 12
- 3.5 USB Interface 13
- 3.5.2 Startup/Enumeration 14
- 3.5.3 Reset 14
- 3.6.1 Endpoint Buffer 15
- 3.6.2 Decoupler 15
- 3.6.3 Audio Buffering Scheme 16
- NUM_USB_CHAN_OUT 17
- NUM_USB_CHAN_IN 17
- 3.8 Audio Driver 19
- Figure 12: 20
- Ports and 20
- (CODEC slave) 20
- 3.9 Digital Mixer 21
- 3.9.1 Control 22
- 3.9.2 Host Control 22
- 3.10 S/PDIF Transmit 24
- 3.10.1 Clocking 25
- 3.10.2 Usage 25
- 3.11 S/PDIF Receive 26
- 3.11.1 Integration 27
- 3.12 ADAT Receive 28
- 3.13 Clock Recovery 29
- 3.14 MIDI 29
- 3.17 Resource Usage 31
- · S/PDIF Transmitter or MIDI 32
- 3.18.1 Port 32A 33
- 3.18.2 Clocking 33
- Codec 34
- 3.18.3 HID 35
- - D SPDIF =0 36
- - D MIDI =1 36
- - DAUDIO_CLASS =1 36
- 3.19.2 CODEC Configuration 37
- 3.19.3 U-Series ADC 37
- 3.19.4 HID Example 38
- SPDIF as zero: 39
- MIDI as 1: 39
- -DNUM_USB_CHAN_IN=0 39
- Software 40
- //# d efine CODEC_SLAVE 1 41
- 4 Programming Guide 43
- 4.2 Code Structure 44
- 4.3.1 Custom Defines 45
- 4.3.2 Configuration Functions 47
- 4.3.3 The main program 49
- 4.4 Adding Custom Code 51
- 5.1 Custom Defines 53
- 5.3 Component API 55
- USB Audio Design Guide 62/61 62
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