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The software layout is the identical to the single tile L-Series Reference Design and

therefore the diagrams Figure 24 and Figure 25 show the software layout of the

code running on the XS1-U chip.

As with the L-Series, each unit runs in a single core concurrently with the others

units. The lines show the communication between each functional unit.

Due to the MIPS requirement of the USB driver (see §3.17), only six cores can be

run on the single tile L-Series device so only one of S/PDIF transmit or MIDI can be

supported.

3.19.1 Clocking and Clock Selection

The actual hardware involved in the clock generation is somewhat diﬀerent to the

single tile L-Series board. Instead of two separate oscillators and switching logic

a single oscillator with a Phaselink PLL is used to generate ﬁxed 24.576MHz and

22.5792MHz master-clocks.

This makes no change for the selection of master-clock in terms of software

interaction: A single pin is (bit 1 of port 4C) is still used to select between the two

master-clock frequencies.

The advantages of this system are fewer components and a smaller board area.

When changing sample frequency, the CodecConﬁg() function ﬁrst puts the CODEC

into reset by setting P4C[2] low. It selects the required master clock and keeps the

CODEC in reset for 1ms to allow the clocks to stabilize. The CODEC is brought out

of reset by setting P4C[2] back high.

3.19.2 CODEC Conﬁguration

The board is equipped with two stereo audio CODECs (Cirrus Logic CS4270) giving

4 channels of input and 4 channels of output. Conﬁguration of these CODECs

takes place using I2C, with both sharing the same I2C bus. The design uses the

open source I2C component sc_i2c

3.19.3 U-Series ADC

The codebase includes code exampling how the ADC built into the U-Series device

can be used. Once setup a pin is used to cause the ADC to sample, this sample is

then sent via a channel to the xCORE device.

On the DJ kit the ADC is clocked via the same pin as the I2S LR clock. Since this

means that a ADC sample is received every audio sample the ADC is setup and it’s

data received in the audio driver core (audio.xc).

The code simply writes the ADC value to the global variable

g_adcVal

for use

elsewhere in the program as required. The ADC code is enabled by deﬁning

SU1_ADC_ENABLE as 1.

http://www.github.com/xcore/sc_i2c

REV 6.1

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